1. Field
Exemplary embodiments of the present invention relate to semiconductor fabrication technology, and more particularly, to a method for fabricating micro patterns of a semiconductor memory device.
2. Description of the Related Art
With the high integration of semiconductor memory devices, it has become difficult to pattern a cell region thereof using a mask process. Thus, a DPT (Double Patterning Technology) process has been applied. Since the DPT process uses a plurality of hard mask layers, the total thickness of the hard mask structure increases. In a peripheral region, however, the thickness of the hard mask structure is to be reduced, in order to form a shallow junction therein.
When the cell region and the peripheral region are separately patterned for such a reason as mentioned above, the numbers of masks and process steps increase. Furthermore, one region patterned first may be damaged by a following process for patterning the other region.